Turning to FIG. 1, an example of a conventional system 100 can be seen. In this system 100, hosts 102-1 to 102-N (which can be; for example, a computer, router, or switch) are able to communicate with one another over communications medium 112 (which can; for example, be an optical fiber, backplane, or twisted pair) through network interfaces 104-1 to 104-N. In this example, the network interfaces 104-1 to 104-N employ Ethernet over Electrical Backplanes and, more specifically, 10 GBase-KR. A description of 10 GBase-KR can be found in the Institute of Electrical and Electronics Engineers (IEEE) standard 802.3-2008 (which is dated Dec. 26, 2008 and which is incorporated by reference herein for all purposes). These network interfaces 104-1 to 104-N employ media access control (MAC) circuits 106-1 to 106-N that communicate with PHYs 110-1 to 110-N via media independent interfaces (MIIs) 108-1 to 108-N (which can typically have half-duplex or full-duplex operation). Each of which is described in IEEE standard 802.3-2008.
Of interest here, however, are PHYs 110-1 to 110-N, and, as can be seen in greater detail in FIG. 2, PHYs 110-1 to 110-N (hereinafter PHY 110), PHY 110 employs several sublayers. This PHY 110 can be an independent integrated circuit (IC) or can be integrated with a MAC circuit (i.e., MAC circuit 106-1) and an MII 108. As shown, the PHY 110 is generally comprised of physical medium dependent (PMD) sublayer logic 212; physical medium attachment (PMA) sublayer logic 210, forward error correction (FEC) sublayer logic 204, and physical coding (PCS) sublayer logic 202. These sublayer logic circuits 202, 204, 210, and 212 interact with one another to provide communications between MII 108 and communications medium 112. For transmission, the FEC sublayer logic 204 employs an encoder 206 as described in IEEE standard 802.3-2008, clause 74, and, for reception, the FEC sublayer logic 204 employs a decoder 308 as described in IEEE standard 802.3-2008, clause 74.
As can be seen in FIG. 3, the PCS sublayer logic 202 can be a transceiver, having a PCS transmitter 302 and a PCS receiver 304. The transmitter 302, in this example, is able to receive data from MII 108, encode the data with encoder 306, scramble the encoded data with scrambler 308, and convert (so as to be used by FEC sublayer logic 204) with gearbox 310. The receiver 304, in this example, is able to convert data from FEC sublayer logic 204 using gearbox 312, descramble the data with descrambler 314, and decode the data (for use with MII 108) with decoder 316. The details of PCS sublayer logic 202 can, for example, be seen in IEEE standard 802.3-2008, clauses 48 and 74.
Looking to the gearbox 310 (an example of which can be seen in greater detail in FIG. 4); it is able to perform data conversion over different clock domains. For example, the gearbox 310 can receive input data payloads (which can, for example, be 66 bits wide) at a clock rate (e.g. 161.13 MHz) in one domain and covert the data into payloads to output data payloads (which can, for example, be 16 bits wide) at another clock rate (e.g., 644.53 MHz), in another clock domain. To do this, input data DATAIN is provided to multiplexers 404-1 and 404-2 (which, as shown, are controlled by write pointer 402). This allows the input data DATAIN to be input into first-in-first-out memory (FIFO) 406 (which, typically, has two halves that can each be 66 bits wide). The read pointer 408 and comparison circuit 410 (which is typically a read/write pointer comparison circuit) then can allow the data output DATAOUT to be read out of the FIFO 406 at the clock rate (e.g., 644.53 MHz) of the output domain. Usually the clock signals for each of the domains (i.e., two as shown) are synchronized, but a “stall” is generally needed after a set number of cycles (e.g., 33 cycles) to preserve synchronization.
Gearbox 312 (an example of which can be seen in FIG. 5) performs an analogous function to that of gearbox 310. For example, the gearbox 312 can receive input data payloads (which can, for example, be 16 bits wide) at a clock rate (e.g. 644.53 MHz) in one domain and covert the data into payloads to output data payloads (which can, for example, be 66 bits wide) at another clock rate, (e.g., 161.13 MHz) in another clock domain. This is generally accomplished by the reception of input data DATAIN by the write pointer 502. This input data DATAIN can be written to FIFO 504 (which is, typically, similar in construction to FIFO 406) with the assistance of comparison circuit 510 (which is typically a read/write pointer comparison circuit). The output data DATAOUT can then be read out from FIFO 504 through multiplexer 506 (which is generally controlled by the read pointer 508). With this arrangement, however, clock signals from the domains (i.e., two as shown) are not synchronous.
With each of these gearboxes 310 and 312, there are several problems. Because of the different time domains, timing is particularly complex. Also, largely because of the different time domains, complex read/write pointer circuitry is usually required. Therefore, there is a need for PCS sublayer logic with improved gearboxes.
Some examples of conventional systems are: U.S. Pat. Nos. 7,499,500; 7,873,892; 8,108,756; U.S. Patent Pre-Grant Publ. No. 2009/0276681; U.S. Patent Pre-Grant Publ. No. 2010/0095185; U.S. Patent Pre-Grant Publ. No. 2010/0229067; and “IEEE Standard 802.3ap-2007: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications, Amendment 4: Ethernet Operation over Electrical Backplanes,” IEEE-SA Standards Board, Mar. 22, 2007; and IEEE Standard 802.3-2008 sections 1-5, Dec. 26, 2008 (which has been incorporated by reference above).